1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a clock signal generation circuit.
2. Description of the Related Art
In a semiconductor integrated circuit, dispersion in delay time of the clock signal may occur among plurality of wiring lines, because of changes in phase, duty cycle or the like of the clock signal. This might cause an error in functions of various circuits. Therefore, in a known method (JP H11-194848A), buffers are arranged on the clock signal lines in a tree-like form (referred to as a clock tree hereinbelow) to equalize delay time of the clock signal at circuits to which the clock signal is supplied.
However, when a clock tree with the large number of hierarchy is formed, a logic delay occurs to a cell positioned at the terminal of the clock tree, and access time deteriorates. In addition, since the clock tree structure may increase the area of the semiconductor integrated circuit because it needs buffers therein. Since the conventional art has the above-mentioned problem, it is difficult to provide a small semiconductor integrated circuit with a tolerance against changes in phase, duty cycle or the like of the clock signal.